[PATCH 3/3] arm64: dts: marvell: add description for SDHCI controller in CP110 slave

[Thomas Petazzoni]

The two CP110 blocks present in the Armada 8K are identical, so since
there is an SDHCI controller described in the master CP110
description, it should also be described in the slave CP110.

Signed-off-by: Thomas Petazzoni <***@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 2e6422a..ef95718 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -258,6 +258,16 @@
status = "okay";
};

+ cps_sdhci0: ***@780000 {
+ compatible = "marvell,armada-cp110-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core";
+ clocks = <&cps_clk 1 4>;
+ dma-coherent;
+ status = "disabled";
+ };
+
cps_crypto: ***@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;

[Thomas Petazzoni]

When the conversion of the Marvell CP110 Device Tree description from
using GIC interrupts to using ICU interrupts was done, the RTC on the
slave CP110 was left unchanged. This commit fixes that, so that all
devices on the CP properly get their interrupt through the ICU.

Fixes: 6ef84a827c375 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K")
Signed-off-by: Thomas Petazzoni <***@free-electrons.com>
---
There's no need for a Cc: stable, because the ICU conversion was
merged in 4.13-rc1.
---
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 8c08a64..67936f7 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -64,7 +64,7 @@
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};

cps_ethernet: ***@0 {

[Gregory CLEMENT]

Hi Thomas,

Post by Thomas Petazzoni
When the conversion of the Marvell CP110 Device Tree description from
using GIC interrupts to using ICU interrupts was done, the RTC on the
slave CP110 was left unchanged. This commit fixes that, so that all
devices on the CP properly get their interrupt through the ICU.
Fixes: 6ef84a827c375 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K")

Applied on mvebu/fixes

Thanks,

Gregory

Post by Thomas Petazzoni
---
There's no need for a Cc: stable, because the ICU conversion was
merged in 4.13-rc1.
---
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 8c08a64..67936f7 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -64,7 +64,7 @@
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.9.4

[Thomas Petazzoni]

In both the CP110 master and slave description, the node describing
the RTC was at the wrong place when taking into account increasing
register addresses. Interestingly, it was not even at the same (wrong)
place in both files.

This commit adjusts that, making the master and slave descriptions
more aligned.

Signed-off-by: Thomas Petazzoni <***@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 14 +++++++-------
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 14 +++++++-------
2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 1294d62..394e54d 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -115,6 +115,13 @@
msi-parent = <&gicp>;
};

+ cpm_rtc: ***@284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
cpm_syscon0: system-***@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
@@ -155,13 +162,6 @@
};
};

- cpm_rtc: ***@284000 {
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
cpm_sata0: ***@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 67936f7..2e6422a 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -60,13 +60,6 @@
compatible = "simple-bus";
ranges = <0x0 0x0 0xf4000000 0x2000000>;

- cps_rtc: ***@284000 {
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
cps_ethernet: ***@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
@@ -122,6 +115,13 @@
msi-parent = <&gicp>;
};

+ cps_rtc: ***@284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
cps_syscon0: system-***@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;

[Gregory CLEMENT]

Hi Thomas,

Post by Thomas Petazzoni
In both the CP110 master and slave description, the node describing
the RTC was at the wrong place when taking into account increasing
register addresses. Interestingly, it was not even at the same (wrong)
place in both files.
This commit adjusts that, making the master and slave descriptions
more aligned.

Applied on mvebu/dt64

Thanks,

Gregory

Post by Thomas Petazzoni
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 14 +++++++-------
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 14 +++++++-------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 1294d62..394e54d 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -115,6 +115,13 @@
msi-parent = <&gicp>;
};
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
@@ -155,13 +162,6 @@
};
};
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 67936f7..2e6422a 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -60,13 +60,6 @@
compatible = "simple-bus";
ranges = <0x0 0x0 0xf4000000 0x2000000>;
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
@@ -122,6 +115,13 @@
msi-parent = <&gicp>;
};
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
--
2.9.4

[Gregory CLEMENT]

Hi Thomas,

Hello,
Here are a few updates to the CP110 DT description. The first one is
really a fix, the next two are just improvements.

I was writig the same series and I alreadu sent the same 1st patch!

I will apply your version

Thanks,

Gregory

Thanks!
Thomas
arm64: dts: marvell: use ICU for the CP110 slave RTC
arm64: dts: marvell: re-order RTC nodes in Marvell CP110 description
arm64: dts: marvell: add description for SDHCI controller in CP110
slave
.../boot/dts/marvell/armada-cp110-master.dtsi | 14 ++++++-------
.../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 24 +++++++++++++++-------
2 files changed, 24 insertions(+), 14 deletions(-)
--
2.9.4

[Gregory CLEMENT]

Hi Thomas,

Post by Thomas Petazzoni
The two CP110 blocks present in the Armada 8K are identical, so since
there is an SDHCI controller described in the master CP110
description, it should also be described in the slave CP110.

Actually they are not totally identically and there is no SD/eMMC
controller on the CP slave.

Gregory

Post by Thomas Petazzoni
---
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 2e6422a..ef95718 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -258,6 +258,16 @@
status = "okay";
};
+ compatible = "marvell,armada-cp110-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core";
+ clocks = <&cps_clk 1 4>;
+ dma-coherent;
+ status = "disabled";
+ };
+
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
--
2.9.4