[PATCH v5 0/2] Add Basic SoC support for MT7622

Discussion:

s***@mediatek.com

2017-06-16 17:06:25 UTC

From: Sean Wang <***@mediatek.com>

Changes since v4:
- redefine the two dummy clocks with the correct frequency
which is 25MHz and 280MHz respectively.

Changes since v3:
- get rid of those accepted patches
- rebased to branch v4.12-next/dts64 in Matthias' tree
- fixed uart node in dts with two clocks as described in bindings documentation

Changes since v2:
- merge back required basic clock nodes into the .dtsi file
- update the property of interrupts in timer nodes with 2 CPUs

Changes since v1:
- update SPDX-License-Identifier
- remove next-level-cache property since cache geometry detection was removed since 4.12

This patch set adds basic SoC support for MediaTek MT7622
SoC based on 4.12-rc1.

Sean Wang (2):
arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file
arm64: dts: mt7622: add dts file for MT7622 reference board variant 1

arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 27 +++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 110 +++++++++++++++++++++++++++
3 files changed, 138 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi

--
2.7.4

s***@mediatek.com

2017-06-16 17:06:26 UTC

Permalink

From: Sean Wang <***@mediatek.com>

add basic nodes into the mt7622.dtsi for the system
bring-up which includes ARM CPU, GIC, timer, MediaTek
UART, SYSIRQ and one reserved memory region for ATF.

Signed-off-by: Sean Wang <***@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 110 +++++++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
new file mode 100644
index 0000000..b111fec
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ming Huang <***@mediatek.com>
+ * Sean Wang <***@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt7622";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: ***@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clock-frequency = <1300000000>;
+ };
+
+ cpu1: ***@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ clock-frequency = <1300000000>;
+ };
+ };
+
+ uart_clk: dummy25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ bus_clk: dummy280m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <280000000>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: ***@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
+ no-map;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ sysirq: interrupt-***@10200620 {
+ compatible = "mediatek,mt7622-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200620 0 0x20>;
+ };
+
+ gic: interrupt-***@10300000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10310000 0 0x1000>,
+ <0 0x10320000 0 0x1000>,
+ <0 0x10340000 0 0x2000>,
+ <0 0x10360000 0 0x2000>;
+ };
+
+ uart0: ***@11002000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>, <&bus_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+};

--
2.7.4

s***@mediatek.com

2017-06-16 17:06:27 UTC

Permalink

From: Sean Wang <***@mediatek.com>

Add the support for the MT7622 reference board variant 1 from
MediaTek.

Signed-off-by: Sean Wang <***@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 27 +++++++++++++++++++++++++++
2 files changed, 28 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 015eb07..89371be 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb

always := $(dtb-y)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
new file mode 100644
index 0000000..c08309d
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ming Huang <***@mediatek.com>
+ * Sean Wang <***@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+
+/ {
+ model = "MediaTek MT7622 RFB1 board";
+ compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+
+ chosen {
+ bootargs = "console=ttyS0,115200n1";
+ };
+
+ memory {
+ reg = <0 0x40000000 0 0x3F000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};

--
2.7.4

Sean Wang

2017-07-20 03:02:25 UTC

Permalink

Hi, Matthias

just a gentle ping on this

Sean

Post by s***@mediatek.com
- redefine the two dummy clocks with the correct frequency
which is 25MHz and 280MHz respectively.
- get rid of those accepted patches
- rebased to branch v4.12-next/dts64 in Matthias' tree
- fixed uart node in dts with two clocks as described in bindings documentation
- merge back required basic clock nodes into the .dtsi file
- update the property of interrupts in timer nodes with 2 CPUs
- update SPDX-License-Identifier
- remove next-level-cache property since cache geometry detection was removed since 4.12
This patch set adds basic SoC support for MediaTek MT7622
SoC based on 4.12-rc1.
arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file
arm64: dts: mt7622: add dts file for MT7622 reference board variant 1
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 27 +++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 110 +++++++++++++++++++++++++++
3 files changed, 138 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi

Matthias Brugger

2017-07-20 10:56:06 UTC

Permalink

Post by Sean Wang
Hi, Matthias
just a gentle ping on this

pushed now to v4.13-next/dts64

Thanks!

Post by Sean Wang
Sean